1. Field of the Invention
The present invention relates to a mixer circuit with high linearity and high gain.
2. Description of Related Art
FIG. 9 is a circuit diagram showing a configuration of a conventional cascode mixer circuit with a source connected to a negative feedback impedance element. In FIG. 9, the reference symbol VDD designates a power supply terminal; Z11 designates an impedance element that has a DC path and is connected to the power supply terminal VDD; Z12 designates an impedance element that has a DC path and is connected to the impedance element Z11.
The reference symbol M1 designates a MOSFET having its drain connected to the impedance element Z12; M2 designates a MOSFET having its drain connected to the source of the MOSFET M1; and Zs designates an impedance element that has a DC path and is connected across the source of the MOSFET M2 and a ground terminal. The back gates of the MOSFETs M1 and M2 are connected to the ground terminal.
The impedance elements Z11, Z12 and Zs are each composed of a passive element such as a resistor, capacitor and inductance.
The reference symbol LOin designates an LO (local) signal input terminal connected to the gate of the MOSFET M1; RFin designates an RF (radio frequency) signal input terminal connected to the gate of the MOSFET M2; and IFout designate an output terminal connected between the impedance elements Z11 and Z12.
Next, the operation of the conventional cascode mixer circuit will be described.
The RF input signal fed through the RF signal input terminal RFin is a small signal expressed by ARFINsin (xcfx89RFt). On the other hand, the LO input signal fed through the LO signal input terminal LOin is a large signal expressed by sq(xcfx89LOt) which switches the MOSFET M1.
The output signal IFOUT produced from the output terminal IFout is expressed as follows.                                                                         IF                OUT                            =                              xe2x80x83                            ⁢                              Z11                xc3x97                β                ⁢                                  xe2x80x83                                ⁢                                  A                  RFIN                                ⁢                                  sin                  ⁡                                      (                                                                  ω                        RF                                            ⁢                      t                                        )                                                  xc3x97                                  sq                  ⁡                                      (                                                                  ω                        LO                                            ⁢                      t                                        )                                                                                                                          =                              xe2x80x83                            ⁢                              β                ⁢                                  xe2x80x83                                ⁢                                  Z11A                  RFIN                                ⁢                                  sin                  ⁡                                      (                                                                  ω                        RF                                            ⁢                      t                                        )                                                  xc3x97                                                      (                                          2                      /                      π                                        )                                    [                                                            (                                              π                        /                        4                                            )                                        +                                          sin                      ⁡                                              (                                                                              ω                            LO                                                    ⁢                          t                                                )                                                              +                    …                                    ⁢                                      xe2x80x83                                    ]                                                                                        (        1        )            
where xcex2 is a transconductance of the MOSFET M2 determined by its process and device structure.
The major output signal component SM without the DC component is expressed by the following expression (2).                                                                         S                M                            ≈                              xe2x80x83                            ⁢                                                (                                      2                    /                    π                                    )                                ⁢                β                ⁢                                  xe2x80x83                                ⁢                                  Z11A                  RFIN                                ⁢                                  sin                  ⁡                                      (                                                                  ω                        RF                                            ⁢                      t                                        )                                                  xc3x97                                  sin                  ⁡                                      (                                                                  ω                        LO                                            ⁢                      t                                        )                                                                                                                          =                              xe2x80x83                            ⁢                                                (                                      1                    /                    π                                    )                                ⁢                β                ⁢                                  xe2x80x83                                ⁢                                  Z11A                  RFIN                                xc3x97                                  [                                                            cos                      ⁡                                              (                                                                              "LeftBracketingBar"                                                                                          ω                                RF                                                            -                                                              ω                                LO                                                                                      "RightBracketingBar"                                                    ⁢                          t                                                )                                                              -                                          cos                      ⁡                                              (                                                                              (                                                                                          ω                                RF                                                            +                                                              ω                                LO                                                                                      )                                                    ⁢                          t                                                )                                                                              ]                                                                                        (        2        )            
Thus, two frequency components, the sum and difference components of the RF input signal and LO input signal, are obtained, making it possible to obtain one of them by filtering the output signal IFOUT in an actual application.
One of the causes of the distortion of the mixer circuit as shown in FIG. 9 is the nonlinearity of the drain source transconductance gds of the MOSFET M2, which is given by the following expression (3).                                                                         g                ds                            =                                                                    k                    ds                                                        2                    ⁢                    L                    ⁢                                                                                            V                          DS                                                -                                                  (                                                                                    V                              GS                                                        -                                                          V                              T                                                                                )                                                +                                                  φ                          0                                                                                                                    ⁢                                  I                  Dsat                                                                                                                        I                Dsat                            =                                                β                  2                                ⁢                                                      (                                                                  V                        GS                                            -                                              V                        T                                                              )                                    2                                                                                        (        3        )            
where L is the length of the gate of the MOSFET M2, VGS is the gate-source voltage, VDS is the drain-source voltage, VT is the threshold voltage, "PHgr"o is the built-in voltage, and kds is a constant determined by the process.
Thus, the changes in the drain-source transconductance gds against the drain-source voltage VDS is expressed by the following expression (4), and the distortion becomes large when the drain-source voltage VDS is small.                                           ∂                          g              ds                                            ∂                          V              DS                                      =                                            -                              k                ds                                                    4              ⁢                                                L                  ⁡                                      (                                                                  V                        DS                                            -                                              (                                                                              V                            GS                                                    -                                                      V                            T                                                                          )                                            +                                              Φ                        0                                                              )                                                                    3                  2                                                              ⁢                      I            Dsat                                              (        4        )            
With the foregoing configuration, the conventional mixer circuit has the following problems. First, although the MOSFET M1 determines the drain-source voltage VDS of the MOSFET M2 to which the RF input signal is applied, it is difficult to apply a large bias to the MOSFET M1, particularly when the power supply voltage is small. Thus, it has a problem of increasing the distortion.
In addition, to achieve the high gain, the impedance element Z11 or the gate-source voltage VGS of the MOSFET M2 must be increased. However, operation at the low power supply voltage in these cases will present the following problems. First, increasing the impedance element Z11 will drop the drain potential, which can disable the operation of the MOSFET M2. Second, as for the gate-source voltage VGS, since the bias voltage beyond the power supply voltage is impossible, such a condition as the power supply voltage of 1.0 V and the threshold voltage VT of 0.35 V cannot achieve a large gain.
The present invention is implemented to solve the foregoing problems. It is therefore an object of the present invention to provide a mixer circuit capable of achieving high linearity and high gain even at a low power supply voltage.
According to a first aspect of the present invention, there is provided a mixer circuit including a first mixer circuit comprising a first and second MOS transistors connected in cascode; a first impedance element connected to the drain of the first MOS transistor; a first signal input terminal connected to the gate of the first MOS transistor to be supplied with an RF signal; and a second signal input terminal connected to the gate of the second MOS transistor to be supplied with a local signal, wherein a relationship (VG1xe2x88x92VGS2) less than (VGS2xe2x88x92VT1) is established, where VG1 is a bias voltage applied to the gate of the first MOS transistor, VGS2 is a bias voltage applied to the gate of the second MOS transistor, and VT1 is a threshold voltage of the first MOS transistor, the bias voltages VG1 and VGS2 being each defined with respect to the source bias voltage of the second MOS transistor. Here, the first mixer circuit may further comprises a second impedance element connected between the first impedance element and the first MOS transistor; and a third impedance element connected between the second MOS transistor and the ground. Thus, it can increase the drain-source voltage of the first MOS transistor to which the RF signal is supplied, offering an advantage of being able to implement a high linearity and low distortion mixer circuit even under the condition of a low power supply voltage.
According to a second aspect of the present invention, there is provided a mixer circuit including a first mixer circuit having one of the first signal input terminal and the second signal input terminal connected to a back gate of at least one of the first MOS transistor and the second MOS transistor. The first mixer circuit may comprise the above-mentioned second impedance element and third impedance element. It may further comprise a fourth impedance element connected across one of the first signal input terminal and the second signal input terminal and a back gate of at least one of the first MOS transistor and the second MOS transistor. Besides, the first signal input terminal may be supplied with an RF signal, and the second signal input terminal may be supplied with a local signal. Thus, the mixer circuit can reduce the threshold voltage of the MOS transistor, and hence increase the current flowing through the MOS transistors even under the condition of the low power supply voltage, thereby offering an advantage of being able to increase the gain.
Here, the relationship (VG1xe2x88x92VGS2) less than (VGS2xe2x88x92VT1) may be established. Thus, it can increase the drain-source voltage of the first MOS transistor to which the RF signal is supplied, offering an advantage of being able to implement a high linearity and low distortion mixer circuit even under the condition of a low power supply voltage.
The first signal input terminal may be supplied with a local signal, and the second signal input terminal may be supplied with an RF signal. Thus, the mixer circuit can reduce the threshold voltage of the MOS transistor, and hence increase the current flowing through the MOS transistors even under the condition of the low power supply voltage, thereby offering an advantage of being able to increase the gain.
The first mixer circuit may further comprise a fifth impedance element for connecting one of the first and second signal input terminals to a back gate of at least one of the first MOS transistor and the second MOS transistor, and a third bias circuit for supplying the back gate with a positive bias voltage with respect to the ground. Thus, the mixer circuit can reduce the threshold voltage of the MOS transistor, and hence increase the current flowing through the MOS transistors even under the condition of the low power supply voltage, thereby offering an advantage of being able to increase the gain.
The first mixer circuit may further comprise a switch for supplying the back gate with the positive bias voltage only when the first mixer circuit is in operation, and for short-circuiting the back gate to the second fixed bias point when the first mixer circuit is out of operation. The mixer circuit offers an advantage of being able to reduce the leakage current.
The mixer circuit may further comprise a second mixer circuit with the same configuration as the first mixer circuit, thereby arranging a differential input/output mixer circuit. Thus, it can reduce the distortion. In addition, the differential arrangement, which is often used for the local signal, is advantageous in practical application to achieve the common-mode rejection.
The mixer circuit may further comprise a third impedance element connected between the ground and a common connecting point of two sources of the two second MOS transistors of the first and second mixer circuits. The common connecting point may be connected directly to the ground. Thus, it can reduce the distortion. In addition, the differential arrangement, which is often used for the local signal, is advantageous in practical application to achieve the common-mode rejection.